Senior IP Design Verification Engineer

[ad_1]
Job title: Senior IP Design Verification Engineer

Company:

Job description: on System Verilog, familiar with OVM/UVM methodologies and Perl Script. Python is an added advantage. Passionate…

Expected salary:

Location: Pulau Pinang

Job date: Thu, 08 Aug 2024 22:09:55 GMT

Apply for the job now!
#Senior #Design #Verification #Engineer

Related Posts
1 of 2,683

[ad_2]

Leave a comment

This website uses cookies to improve your experience. We'll assume you're ok with this, but you can opt-out if you wish. Accept Read More

Skip to toolbar