PCIe5.0 / USB4 PHY Architect

Job title: PCIe5.0 / USB4 PHY Architect

Company:

Job description: building blocks for High-Speed Interfaces, SERDES,PLL, CDR, RTL logic design, Synthesis, Physical design, Power analysis…/SystemVerilog, Static timing analysis concepts, APR, Floor-planning, Metal-routing, Power- grid andArchitecture specification…

Expected salary:

Location: Petaling Jaya, Selangor

Job date: Thu, 05 Sep 2024 22:56:48 GMT

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#PCIe50 #USB4 #PHY #Architect